1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a chain gate line structure, which can reduce the contact resistance of a DRAM cell by increasing the active regions of the cell.
2. Description of Related Art
As the design rule of semiconductor devices gets smaller and become highly integrated, the size of the memory cell, such as a DRAM or the like, is gradually decreasing. For the high integration of semiconductor devices, researches on new materials associated with lithography, a cell structure, and wiring and physical properties researches associated with insulating films and the like are required, as well as research for increasing the contact critical dimension (CD) of a gate line, a bit line, and a capacitor.
FIG. 1 is a plan view showing a gate line structure and a contact structure of a semiconductor device in the prior art. FIG. 2 is a vertical cross sectional view of FIG. 1.
Referring to FIGS. 1 and 2, in a semiconductor device, such as a DRAM or the like having a gate line according to the prior art, device isolation films 12, such as shallow trench isolation (STI) films, for isolating active regions and inactive regions are formed on a semiconductor substrate 10. Gate electrodes 14 made of doped polysilicon, metal silicide, and the like are formed on top of the semiconductor substrate 10. Masks 16 made of insulating material are formed on top of the gate electrodes 14, and spacers 18 made of insulating material are formed on the side walls thereof. There is formed a landing plug 20 which is contacted perpendicularly to active regions of the substrate 10 and a bit line or storage nodes through a contact hole in an interlayer insulating film gap-filling the space between the spacers 18.
Though not shown in the drawings, a planarized interlayer insulating film is formed on the entire resultant material. A bit line connected to the landing plug 20 is formed thereon. Another planarized interlayer insulating film is formed on the entire resultant material having the bit line. Storage node contacts connected to the landing plug 20 are formed through a contact hole of the interlayer insulating film.
As shown in FIG. 1, the semiconductor device, such as a DRAM or the like, having such construction according to the prior art has a structure in which gate lines of gate electrodes 14 are arrayed in series. At this point, reference numeral 10 of FIG. 1 denotes active regions of the semiconductor substrate in which no device isolation films are formed.
However, as the size of a DRAM cell gets smaller, the contact surface area between the landing plug 20 and the active regions of the semiconductor substrate 10, which makes the contact resistance larger and larger. Consequently, an increase in contact resistance of a cell is causing weakening of the tWR (time of Writing Recovery) property desired by a DRAM cell.